1. Field of the Invention
The present invention relates to capacitors of a semiconductor device and to a manufacturing method thereof, and more particularly to capacitors with a dielectric made of ferroelectric materials for increasing the capacitance thereof. The present invention is also concerned with a method of manufacturing the capacitors.
2. Discussion of Related Art
With the higher integration and use of semiconductor devices, research has focused on increasing the capacitance density of a capacitor so as to maintain the capacitance of such capacitors at an acceptable value regardless of the reduction in the cell size. In order to increase the capacitance of the capacitor, a stacked capacitor or a trench capacitor has been used since it can provide a dielectric with a large surface area. However, there still remains the problem that the increase of the surface area of the dielectric is limited due to the complicated manufacturing process of the stacked capacitor or the trench capacitor.
Therefore, it has been proposed to increase the capacitance of the capacitor by making the dielectric with a ferroelectric material, such as Ta.sub.2 O.sub.5, PZT(Pb(Zr Ti)O.sub.3), or BST((Ba Sr)TiO.sub.3).
FIGS. 1(A) to 1(D) are diagrams showing the manufacturing process of a capacitor according to the prior art.
Referring to FIG. 1(A), a transistor is formed within an active region limited by a filled oxide layer 13 on a semiconductor substrate 11. The transistor includes a gate electrode 19 and source and drain regions 15 and 17. A bit line 23 is formed to be in contact with the drain region 17. An insulating layer 21 is formed over the whole surface of the resultant structure, and an insulating layer 25 made of silicon oxide is formed over the insulating layer 21.
After the formation of an etch stop layer 27 over the insulating layer 25, a predetermined portion of the etch stop layer 27 and insulating layers 25 and 21 are removed by photolithography, thus forming a contact hole 29 to expose the source region 15.
Referring to FIG. 1(B), a first conductive layer 31 is formed on the etch stop layer 27 and is in contact with the source region 15 by filling the contact hole 29. The first conductive layer 31 is formed by thickly depositing polycrystalline silicon doped with impurities using the Chemical Vapor Deposition method (hereinafter referred to as "CVD"). After deposition of a silicon oxide layer over the first conductive layer 31, the silicon oxide is patterned to form a mask pattern 33 corresponding to the contact holes 29. Thereafter, silicon nitride is deposited over the first conductive layer 31 and the mask pattern 33 using CVD and then is etched to form a side wall 35 at the sides of the mask pattern 33.
Referring to FIG. 1(C), the first conductive layer 31 is etched to expose the etch stop layer 27 by using the mask pattern 33 and side wall 35 as a mask. Thereafter, the remaining first conductive layer 31 is exposed by removing the mask pattern 33, and the exposed first conductive layer 31 is etched to a predetermined thickness by using the side wall 35 as a mask. In this case, the etch stop layer 27 serves to prevent the insulating layer 25 from being removed while removing the mask pattern 33. Thereafter, the remaining side wall 35 over the first conductive layer 31 is removed. At this time, the exposed portion of the etch stop layer 27 is also removed. The remaining first conductive layer 31 becomes a storage electrode.
Referring to FIG. 1(D), the ferroelectric material, such as for example, Ta.sub.2 O.sub.5, PZT(Pb(Zr Ti)O.sub.3), or BST((Ba Sr)TiO.sub.3) is deposited over the surface of the first conductive layer 31 and is then thermally processed, thus forming a dielectric layer 37. Thereafter, polycrystalline silicon doped with impurities is deposited over the dielectric layer 37, thus forming a second conductive layer 39 which is used as a plate electrode.
However, the conventional capacitor manufacturing method as described above has the problem that the surface of the first conductive layer used as a storage electrode is oxidized by the oxygen constituting the dielectric layer and thus the dielectric layer becomes thick, reducing its capacitance. An additional problem is that the planarization of the second conductive layer deteriorates due to the first conductive layer.